Oh, I learned today that VHDL has (had?) a standardization group called VASG, which is quite a nested acronym:

VASG → VHDL Analysis and Standardization Group → VHSIC Hardware Description Language Analysis and Standardization Group → Very High Speed Integrated Circuit Hardware Description Language Analysis and Standardization Group

Take a look at Chisel (http://chisel.eecs.berkeley.edu)... they call it a "Hardware Construction Language" instead of a HDL, as you describe how the hardware works in chisel code, which is just a Scala embedded language. It is then able to generate FPGA or VLSI optimized verilog, and a C++ cycle accurate simulator. I have been using it for the past ~9 months designing a new chip.

What is your experience with Chisel? How much more productive are you compared to writing Verilog?

I am interested in trying out new tools, but information on Chisel is pretty sparse.

Yes but you can also build functional or cycle accurate simulator in software which can give you some information on how the processor could potentially perform. Of course having a soft-core running on an FPGA will most likely give you a more accurate idea of how the processor actually works.

Also, some instructions of modern CPUs are implemented in software that resides on the CPU.

http://en.wikipedia.org/wiki/Microcode

Microcode is old.. So 'modern CPUs' --> 'some CPUs'.

C++ (possibly abusing the preprocessor to abuse the templating system...)