Why do you think it's necessary to debug signal layers by physically connecting to them (other than the I/O pins of the chip)? The only time you would actually try to connect to a chip other than through the I/O pins is in an adversarial situation.
It's not usually necessary, but they do in fact have this capability and do use it for testing and failure analysis (I think it is mostly used for debugging fabrication issues, where physically seeing the construction of the chip is important). The other amazing thing they can do is some level of rework: creating or removing connections to test a change or hypothesis without the expensive process of making a new mask for that layer. There's a video from intel's testing lab where the leader brags he can take a chip with a single failed transistor somewhere in it, and give you a picture of it.
Typically failed transistors are identified by the DFT scan chain. After the logic is netlisted (meaning, they create a giant list of flops, gates, and the wires that connect them), the DFT tooling adds additional inputs to each flop that let it be controlled by a sideband signal, as a giant shift register. So you can put the chip in DFT mode and set all the flops to a known pattern. Run the clock a few cycles and you know what state the chip should be in (because you can simulate it). So you scan that giant shift register back out and check for differences.
This process is automated, and for a given chip you might have a few gigabytes of stimulus total, which can collectively identify a single failed transistor (and kick that part out of the batch).
Now, I have no idea how you take a picture of a bad transistor. That's beyond me.
If not, I would intuitively think this whole approach would fail?